1-D DCT Using Latency Efficient Floating Point Algorithms

Viswanath Gowd A, Yedukondala Rao V, T. Shanmuganantham

Abstract


This paper presents the design of one-dimensional discrete cosine transform (DCT) architecture for digital signal processing (DSP) applications. DCT is a basic transformation for coding method which converts spatial domain to frequency domain of image. In 1-D DCT operation addition, subtraction, multiplication operations are required. These operations must be accurate, less latency. Floating point operations have dynamic range of representation, more accurate and perform millions of calculations per second. So the floating point operations are used for the above operations. In this floating point adder/subtractor is the most complex operation in a floating-point arithmetic and consists of many variable latency- and area dependent sub-operations. In floating-point addition implementations, latency is the primary performance bottleneck. So different types of floating point adder/subtractor algorithms such as LOD, LOP, Two-path are used to decrease the latency. The trade off is observed in 1-D DCT by changing different types of adders in place of summer. All architectures are designed and implemented using VHDL using Xillinx 13.1software.


Keywords


DCT, Floating point operations, FPGA

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