Network Simulation and Synthesis of 2D Mesh Topological structure in HDL (Hardware Description Language) environment with Network on Chip (NOC)

Simmi Aggarwal, Mala Aggarwal

Abstract


In our research of architectural template, called network on chip architecture, for developing large and complex systems on a single chip, we introduced the implementation of 2D mesh topological structure. The architecture supports physical level and architectural level design integration. Basic communication mechanism between resources is envisioned to be packet switched message passing through the switches. NOC architecture defines four layered inter-resource communication protocol (physical, data-link, network and transport layer), which are adapted from OSI standard. These protocols must be implemented in the resource to network interface (RNI) for every resource in NOC. We have also described a two-phase design methodology for developing systems for the proposed NOC architecture. Speed and size are two important factors while designing the electronic system. It’s Speed of operation and flexibility to modify, measures the performance of the system operation. Traffic handling capacity is an important element of service quality and will therefore play a basic role in this choice Microprocessor/microcontroller (MPMC) system can handle sequential operations with high flexibility and use of Field Programmable Gate Array (FPGA) can handle concurrent operations with high speed in small size area. So combined features of both these systems can enhance the performance of the system. Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. In addition to their usefulness as mentioned above, their internal structure also makes them as a suitable vehicle to learn all aspects of VLSI design because they consist of combinational logic in the form of LUT (look up table), flip-flops as sequential building blocks, and memory for programmability. VLSI design requires a careful forethought about the entire design process with special attention to floor planning, layout, routing, transistor sizing, clock and power distribution and timing analysis. In my proposed research, we have taken the case of mesh topological structure for 2D network having configuration (8 × 8). We developed our design in Xilinx 13.2 VHDL software, and functional simulation in Modelsim 10.1 b, student edition. We optimized all the hardware parameters like size, cost and timings, which can be a boon definitely for large scale network system design like telecommunication switching and wireless sensor networks.

Keywords


NOC= Network on chip SOC = System on chip FPGA = Field programmable gate array VHDL = Very high speed integrated circuit hardware description language VLSI = Very large scale of integration

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