A comparative study on FPGA based FIR filter using broadcast structure and overlap save method

Sumit Kumar Maity, Madhusudan Maiti


Many computation-intensive iteration or recursive application commonly found in digital signal processing and image processing applications uses digital filter as basic components. In this paper we focus on designing digital filter which confine a signal into a prescribed frequency band. The work concentrates at first on the development of the low pass finite impulse response (FIR) digital filter using Mat-Lab FDA tool then we designed the different methodologies for the implementation for the of the FIR filter. We have designed the broad cast structure and the overlap save method. We have tested our algorithm using the Xilinx synthesis tool and then implemented on Spartan 3 family xcs40001-4fg900 FPGA device. The experimental results shows that overlap save structure can be operated in less frequency of 57.382 MHz in comparison to the 155.569 MHz operating frequency of the broadcast structure.




Liang-Fang Chao Edwin Hsing-Mean Sha ―unfolding andretiming data flow DSP Program for RISC multiprocessor scheduling” IEEE International Conference on Acoustics,Speech, and Signal Processing, 1992. ICASSP-92 Vol 5, 1992.

TimothyW. O„Neil Edwin H.-M. Sha ―Rate optimal graph transformation via Extended retiming and unfolding‖, Proceedings of the IASTED International ConferenceParallel and Distributed Computing and Systems (PDCS ’99) Nov 3-6,1999 – Cambridge, MA, USA.

Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu,‖Design optimization and space minimization considering timing andcode size via retiming and unfolding” Microprocessors andMicrosystems, Volume 30, Issue 4, Pages 173-183, 6 June 2006.

Timothy W. O'Neil , Edwin H.-M. Sha ―Combining Extended retiming and unfolding for rate optimal graph transformation‖ Journal of VLSI Signal Processing Systems,Volume 39 Issue 3, March 2005.

T. W. O'Neil , and E. H.-M. Sha ―Optimal graph transformation using extended retiming with minimal unfolding‖ in the Proceedings of the IASTED International Conference on Parallel and Distributed Computing Systems, Las Vegas, NV, November, 2000, pp. 128-133.

José Monteiro, Srinivas Devadas, Abhijit Ghosh‖Retiming sequential circuit for low power‖ Proceedings of the IEEE/ACM international conference on Computer-aided design, ICCAD '93.

Santosh Chede , Kishore Kulat , Rajesh Thakare ―A significance of VLSI Technique for low power real Time system‖ 2010 International Journal of Computer Applications (0975 - 8887),Volume 1 – No. 22.

Mandeep Kaur, Vikas Sharma ―Analysis of various algorithm for low power consumption in embedded system using different architecture‖ International Journal of Electronics Engineering, 2(1), 2010,

Full Text: PDF


  • There are currently no refbacks.


All Rights Reserved © 2012 IJARCSEE

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 Unported License.