LOW POWER IMPLEMENTATION OF OPTIMUM COMPOSITE FIELD ARCHITECTURE WITH MINIMAL AREA FOR HIGH-TROUGHPUT AES S-BOXES

Vasili Supraja, P. Mahesh Kannan

Abstract


In this work, we derive novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF (((22)2)2). After a sequence of algorithmic and architectural optimization processes a best design is selected. The isomorphic mapping with minimal implementation area and cost functionis chosen for implementation after the exploitation of new common sub expression elimination algorithm.Existing System Performs the 8-bit Galois Field inversion of the S-box using subfields of 4 bits and of 2 bits. This work describes a refinement of this approach that minimizes the circuitry, and hence the chip area, required for the S-box with high speed of operation for applications using larger chips. Through the exploitation we achieved 47.91% area improvement and 11.49% improvement in total power consumption.


Keywords


AES(Advanced Encryption Standard), S-Box(Substitution Box), CFA(Composite Field Arthmetic), GF(Galios Field), ANF(Algebraic Normal Form).

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