Efficient FPGA Implementation of FIR Filter Bank Based on Sampling Frequency Decimation

Samane Vahidi, Masoud Mardani

Abstract


This paper is the study of efficient FPGA implementation of FIR (Finite Impulse Response) filter bank based on sampling frequency decimation and it is compared with conventional way of implementing filter bank in FPGA. Digital filters are essential parts in digital communication receivers. In conventional method several filters are designed in the same sampling frequency while in new structure which is presented in this paper, filters are categorized due to their bandwidths and each category is designed in a specific sampling frequency. The design is implemented in VHDL code using Xilinx Vivado software. The result shows that implementing of narrow bandwidth filters in lower sampling frequency benefits two advantages, include optimal FPGA resources and more accurate responses.

Keywords


digital communication receiver, embedded systems, filter bank, FIR, FPGA

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