Efficient FPGA Implementation of FIR Filter Bank Based on Sampling Frequency Decimation

Samane Vahidi, Masoud Mardani


This paper is the study of efficient FPGA implementation of FIR (Finite Impulse Response) filter bank based on sampling frequency decimation and it is compared with conventional way of implementing filter bank in FPGA. Digital filters are essential parts in digital communication receivers. In conventional method several filters are designed in the same sampling frequency while in new structure which is presented in this paper, filters are categorized due to their bandwidths and each category is designed in a specific sampling frequency. The design is implemented in VHDL code using Xilinx Vivado software. The result shows that implementing of narrow bandwidth filters in lower sampling frequency benefits two advantages, include optimal FPGA resources and more accurate responses.


digital communication receiver, embedded systems, filter bank, FIR, FPGA


Kesh Bakhru, Communications receiver design using digital processing, Digital signal processing, Volume 2, Issue 1, January 1992, pages 2-13, 1051-2004(92)90018-T

V. Jayaprakasan, M. Madheswaran, FPGA Implementation of FIR based Decimation Filter Structure for WiMAX Application, International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 7, July 2013

Jinalkumari K. Dhobi, Dr. Y. B. Shukla, Dr. K.R.Bhatt, FPGA Implementation of Fir Filter using Various Algorithms: A Retrospective, International Journal of Research in Computer Science, 4 (2): pp. 19-24, March 2014. doi: 10.7815/ijorcs.42.2014.081

S. Dhabu, A. Ambede, Smitha K. G., S. Darak, A. P. Vinod, Variable Cutoff Frequency FIR Filters: A Survey, arXiv:1804.02891, Apr 2018, [unpublished]

Xilinx, Inc.,FIR Compiler v7.2, LogiCORE IP Product Guide, PG149, November 18, 2015

A. Ammar, M. Julboub, A. Elmghairbi, Digital Filter Design (FIR) Using Frequency Sampling Method, university Bulletin – ISSUE No.15 – Vol. 3- 2013

E. Punskaya, Design of FIR Filters. University of Columbia (2005). http://www.sigproc.eng.cam.ac.uk/~op20, [unpublished]

A. Illa, N. Haridas, E. Elias (2016), Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay, Engineering Science and Technology, an International Journal, Volume 19, Issue 3, Pages 1160-1165, ISSN 2215-0986, doi.org/10.1016/j.jestch.2015.12.010.

SumedhDhabu, A. P. Vinod, Design and FPGA implementation of reconfigurable linear-phase digital filter with wide cutoff frequency range and narrow transition bandwidth, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, issue 2, pp. 181-185, Feb. 2016.

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